Company Name: Intel Technology India Private
Limited
Job Description: Physical Design Engineer
Job reference: 715683
Work Experience: 5 – 6 Years
Work Location: Bangalore
Education: UG - B. Tech/B.E. -
Electronics/Telecommunication
PG - Any Postgraduate
DOCTORATE - Doctorate Not Required
Job Description
Creates bottoms-up elements of chip design
including but not limited to FET, cell, and block-level custom layouts,
FUB-level floor plans, abstract view generation, RC extraction and
schematic-to-layout verification and debug using phases of physical design
development including parasitic extraction, static timing, wire load models,
clock generation, customer polygon editing, auto-place and route algorithms,
floor planning, full-chip assembly, packaging, and verification. Troubleshoots
a wide variety up to and including difficult design issues and applied
proactive intervention. Schedules, staffs, executes and verifies complex chips
development and execution of project methodologies and/or flow developments.
Requires expansive knowledge and practical application of methodologies and
physical design.
Desired Profile
BE in Electronics
Must have 5-6 Years of Relevant experience
Consistent track record as Layout lead. Works
efficiently on Family / Full chip layout - floor plan, Power grid planning.
Could expand to SD / APR
Drives methodological improvement on layout.
Work effectively with Stakeholders and communicate constraints effectively and
proposes solutions.
Technically drive a complete layout project.
Able to identify tasks, milestones, deliverables, and schedules for a project.
Co-ordination of tasks of junior team members, assuring quality of team
deliverables is required.
Impact is IP level
Understanding of the IP level architecture,
signal flow to aid in floorplanning
Website: http://www.intel.com