Company Name: Synapse Techno Design Innovations Private Limited
Job Description: Design Verification (DV) Engineer - Synapse Design
for verilog ASIC/SOCsystem verovm uvm vmm
Job reference: DVEng
Work experience: 4 – 8 Years
Work location: Bangalore
Education: UG - B. Tech/B.E. - Any Specialization
PG - M. Tech - Any Specialization
DOCTORATE - Any Doctorate - Any Specialization, Doctorate Not Required
Job Description
Create verification plans for SoC / IP level verification.
Create test benches in System Verilog.
Write test cases in C / C++, Assembly, e / SV etc.
Utilize advanced verification methodologies like VMM / OVM / UVM / eRM
for writing verification environments.
Expertise in standard IP blocks and protocols such as PCIe, USB 3.0,
SATA, Ethernet, TCP/IP, IPSec, iSCSI, DDR3.
Extensively worked on debugging tests in RTL / GLS both at SOC and IP
level.
Worked on generating code / functional coverage and analyzing the
results.
Low power verification techniques using industry standard tools.
Worked on writing assertions using standard languages.
Write tools and scripts in Perl and other scripting languages to
enhance the verification process.
Excellent problem solving and debugging skills.
Desired Skills: Working knowledge of e / SV is must and exposure to C
/ C++ is a plus.
Experience in writing BFMs, protocol checkers etc is plus.
Working knowledge of ARM-based processors and AMBA bus protocols is a
plus.
If interested please forward you’re updated resume ASAP, with the
below details and also please refer your friends & colleagues as well
Relevant experience:
Current CTC:
Expected CTC:
Notice Period:
Available time to meet us:
Contact Details: Mr. Jayaprakash
Synapse Techno Design Innovations Private Limited, Ferns Icon,
Mezzanine and First Floor, Near Doddankundi Bus Stop, Outer Ring Road, Maratahalli,
Bangalore - 560037
Email: jayaprakash@synapse-da.com
Website: http://synapse-da.com/
