Company Name: Intel Corporation
Job Description: APD SOC
Integration Engineer
Job Number: 702668
Description
Job Description: Creates bottoms-up elements of chip design including
but not limited to FET, cell, and block-level custom layouts, FUB-level floor
plans, abstract view generation, RC extraction and schematic-to-layout
verification and debug using phases of physical design development including
parasitic extraction, static timing, wire load models, clock generation,
customer polygon editing, auto-place and route algorithms, floor planning,
full-chip assembly, packaging, and verification. Troubleshoots a wide variety
up to and including difficult design issues and applied proactive intervention.
Schedules, staffs, executes and verifies complex chips development and
execution of project methodologies and/or flow developments. Requires expansive
knowledge and practical application of methodologies and physical design.
Qualifications
You must possess the below minimum qualifications to be initially
considered for this position. Preferred qualifications are in addition to the
minimum requirements and are considered a plus factor in identifying top
candidates.
Minimum qualifications:
- Must have a BS in Electrical Engineering or Computer Engineering
- Minimum 5 years experience in RTL2GDS
- Minimum 5 years experience using either Synopsys, or Cadence tools
or simliar
- Minimum 5 years experience with static timing analysis experience on
block and full chip level
- Must have the unrestricted right to work in the US without requiring
sponsorship
Preferred qualifications
- A MS degree in Electrical Engineering or Computer Engineering
- 5+ years experience in Synopsys DC or ICC
- 3+ years experience in static timing analysis on full chip timing
convergence
- 5+ years experience in high complexity SOC design
Job Category: Engineering
Primary Location: USA-Texas, Austin
Full/Part Time: Full Time
Job Type: Experienced
Regular/Temporary: Regular
Apply Before: Ongoing
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