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Intel India is hiring Senior Design Automation Engineer - RTL Verification


Job Description

Sr. Design Automation Engineer (RTL Verification) - 710313

Description

This position is in IDGz HIP Design automation team (HIP DA). HIP DA provides design automation tools, flows and methods for designing world class HIP such as PCIe, DDR, SATA, LDOs, ..etc. In this role, you will be responsible for developing and supporting front-end verification/RTL design flows and techniques to enable HIP design across HIP sites. You will own some of the RTL design flows and be responsible for roadmap, internal/external vendor interaction, developing new concepts/BKMs, establishing user trainings and delivering them across global HIP organization.

Qualifications: 

B.S./M.S. in EE/CS

5+ years design automation experience in developing RTL verification flows/environments/establishing methodologies

Experience in SNPS/Mentor/Cadence front-end verification tools such as VCS/ModelSim/Questa/NC-Sim etc

Verilog/System Verilog experience needed.

Experience in low power verification methodologies using VCS-NLP, Static verification using Spyglass-LP etc highly desirable

Experience in Synopsys core tools or RTL/Gate level power estimation is a plus

Candidate must have strong communication skills and strong motivation for customer support

Ability to multi-task and flexibility to work in global environment needed.

Job Category: Engineering
Primary Location: India-India, Bangalore
Full/Part Time: Full Time
Job Type: Experienced
Regular/Temporary: Regular
Posting Date: Apr 25, 2013
Apply Before: Jul 1, 2013

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