Company Name: Qualcomm India
Private Limited
Job Description: Staff SIM
Engineer /manager (gate Level Simulation)
Work Experience: 8 – 10 Years
Work Location: Bangalore
Job Code: E1919065
Job Description
You will be leading gate level
verification effort of a complex chip, core and/or blocks. You will be
responsible for test architecture/requirement definition, test IO requirements,
gate level simulation bring up, gate level verification, SOC level verification
with timing simulations. You will also be responsible for test pattern
generation, silicon bring up, yield analysis, yield optimization, customer
return analysis and DPPM reduction. You will work with design, verification and
post silicon test team. You will provide technical direction to team, create
and execute project plans
Desired Profile
8+ years experience in
ASIC/System verification/gate level verification/post silicon testing
Strong technical knowledge on
gate level verification and verification environment
Understanding of design
architecture, verification environment
Expertise in verifying complex
designs from system as well as block level, through design flow
Exposure to silicon bring up,
silicon testing , bench and application testing
Experience in VERA/System
Verilog, Modelsim/VCS, DEBUSSY
Prior experience in
leading/managing technical team
Knowledge on project planning
and risk assessment
Excellent communication skills
Knowledge on ATPG and Structural
testing is an added advantage
Website: http://www.qualcomm.co.in
