Company Name: Qualcomm India Private Limited
Job Description: Physical Design Engineer (STA
Specialist)
Job Reference: G1912656
Work Experience: 5-9 Years
Work Location: Bengaluru
Physical Design Engineer (STA Specialist)
Understand RTL designs and prepare block/chip
level timing constraints.
Analyze pre-layout timing and recommend
implementation improvements to the RTL designers.
Analyze post-layout timing, generate timing ECOs
and work closely with layout engineers to achieve block level timing closure.
Work with full-chip team to analyze and resolve
interface timing issues and issues in porting block level constraints at top
level.
Skills/Experience: 5 to 9 years of experience in
Signoff Timing Analysis with a good understanding of Physical Design flow.
Strong experience in timing closure of high
performance processor and/or DSP cores. Good understanding of latch based
designs. Hands-on experience in Synthesis, Timing Models, Logical Equivalence
Check.
Good understanding of CMOS digital circuits.
Proficiency with Synopsys DC & PT tools
Experience in Perl, TCL and shell scripting is
desirable
Experience with HSPICE desirable
Excellent interpersonal & analytical skills
with ability to work independently